It is known in the art that chips are typically mounted in or on wire bond packages. Electrical signal propagation and power transportation between chips and packages are through bond wires which connect the wires on the chips to the wires in the packages. Compared with its traditional counterpart, advanced wire bond package technology has a denser bond wire layout and higher speed. It pushes the application space into Gbps, which is comparable to but less expensive than other package technologies, such as High Performance Glass ceramic (HPGC) package technology, alumina ceramic package technology and organic flip-chip Plastic Ball Grid Array (FCPBGA) package technology.
With the ever-increasing speed and integration level in wire bond packages, the problem of electrical noise on signal propagation is becoming increasingly pronounced. A major noise source in advanced wire bond designs with high density I/Os is electromagnetic (EM) coupling among numerous long and closely laid-out bond wires. The parasitic inductance (L) and capacitance (C) between bond wires are dominant electrical parameters in determining the coupling and the quality of signal transmission in this package technology. Bond wire structures usually are rather complicated. The traditional methods to extract these geometry-based parasitics are either very time-consuming or inaccurate for realistic, large-scale wire bond applications. Therefore, prompt and accurate EM modeling and extraction of high frequency parasitic inductance and capacitance at coupled signal bond wires is critical to noise prediction and electrical signal integrity in high speed high density wire bond packages.
Inductance and capacitance elements are generally included in equivalent circuit models which are fed into circuit simulator such as SPICE to calculate the noise level caused by these Ls and Cs. In the circuit analysis of chip-package-board system, each chip, package and board has its corresponding equivalent circuit model. An equivalent circuit models is more like a black box which incorporates the signal transmission properties of the circuit. By simulating the cascaded equivalent circuit models from the chip, package and board, the electrical noise and signal integrity of the entire chip-package-board system can be determined. Each equivalent circuit model typically consists of multiple ‘sub-models’ representing portions of the circuit. The intent of electromagnetic (EM) modeling of the bond wires in advanced wire bond packages is to create an equivalent circuit model of the bond wires which can then be sequentially connected to the equivalent circuit models of the rest portion of the package, the chip and the board for the circuit analysis of the whole system.
With the ever-increasing speed and integration level in wire bond packages, the problem of electrical noise is becoming increasingly pronounced. A major noise source in advanced wire bond designs with high density I/Os is electrical coupling among numerous long and closely laid-out bond wires. The parasitic inductance and capacitance between bond wires are dominant electrical parameters in determining the coupling and the quality of signal transmission. Prompt and accurate modeling and extraction of high frequency parasitic inductance and capacitance at coupled signal bond wires is critical to noise prediction and electrical signal integrity in high speed high density wire bond packages.
Equivalent circuit models of the bond wires can be described by S parameters or SPICE like circuits extracted from full wave three dimensional (3D) EM simulation tool like HFSS for the best accuracy. This type of tools requires the definition of EM ports to introduce EM waves as sources and then solve Maxwell electromagnetic equations through numerical computation in user-specified space with the considerations of 3D propagation of electromagnetic waves and the full range of frequency points from DC to as high as user specified maximum frequency. The results from these tools are equivalent circuit models which describe the EM wave propagation among ports, typically in the form of S parameters (scattering parameters) or SPICE like circuits consisting of a plurality of resistance (R), inductance (L) and capacitance (C) elements. R, L, C elements are obtained by matching S parameters at the ports. Full wave 3D EM simulation is the most accurate EM analysis tool in bond wire modeling. However, some well known disadvantages of the above numerical computation method include long runtime, typically in the order of 3 to 4 hrs for a group of several bond wires. Considering the number of possible bond wire structures to model in a wire bond package, it is impractical to adopt full wave 3D simulation tool for the analysis of the bond wires for the entire package. Another disadvantage is that it requires high level of EM knowledge and simulation experience for each analysis, which package designers are usually not equipped with. The third disadvantage is the convergence problem inheriting in numerical computation which leads to a longer time for a successful run.
Another widely used method to model bond wires is to extract lumped inductance L and capacitance C by simple empirical formulae. The empirical formulae provide lumped self inductance and capacitance as well as mutual inductance and capacitance between two bond wires, based on the most basic geometric parameters such as diameter of cross-section of wires, length, and spacing between two wires. Each bond wire is represented as one lumped LC segment which can be connected with circuitry from the rest of the package. Opposite to the EM simulation method, empirical formulae are calculated very fast. However, these formulae can only be developed over relatively simple geometries of the bond wires. With the inherent complexity in bond wire structures, for example, the existence of multiple signal and ground wires in calculation, wires with different length and curvature etc., the models obtained by applying these formulae on realistic wire bonding designs are usually not accurate.
Quasi-static 3D modeling is a third methodology for modeling bond wires. It differs from full wave 3D EM simulation in that it only simulates at one frequency point. It may require complicated mesh generation procedure like full wave 3D EM simulation or compute LC by simple formula. Therefore, the method could have runtime problem as in a full wave 3D EM simulation or may be too simplistic to handle realistic high speed signal transition on bond wires. Therefore a methodology is needed to fast and accurately model bond wires for the analysis of realistic high speed and high density wire bond designs.
Referring to FIG. 1, a top view of a prior art wire bond package is shown in which the die (chip) is on top of the package (11). FIG. 2(a) is a top-down view illustrating a portion of the prior art wire bond design shown in FIG. 1. Chip (13) is preferably mounted at the center of the package and connected to the package through bond wires (12) from the die pads (21 and 22) at the edge of the chip to the bond finger pads (26 and 27) on the top metal layer of the package. Signals and power systems for a wire bond integrated circuit package are all delivered along the bond wires. Shown in FIG. 2(a) are inner die pad row (21) and outer die pad row (22) staggered by about half-pad pitch. Likewise, bond finger pads on the package are also distributed in an inner bond finger row (26) and an outer bond finger row (27) with much larger spacing between rows and larger pad pitch than those of the die pads. It is noted that some designs have only one die pad row, and others may have only one bond finger pad row. Between chip edge and inner bond finger pads, there are three rings of metal planes on package, designated by the landing of GND (23), VDD (24) and VDD (25) power systems from chip in a typical wire bond package design. Some designs may only have one or two rings.
FIG. 2(b) shows a schematic side view of the structure shown in FIG. 2(a). Die pads (21, 22) are higher than bond finger pads by the height of the die (28). In order to avoid electrical shorts, bond wires, referenced as loop 2, are connected to inner die pads and are higher than those linked to the outer die pads, referenced as loop 1. In addition, the large spacing among power/ground rings (23, 24, 25) and bond finger pad rows (26, 27), as well as the large pitch between the bond finger pads, contribute to avoid electrical shorts. In some design rules, it is permitted that bond wires starting from any die pad row can be connected to any bond finger pad row. Signal wires are usually laid out in an inner die pad row. Power/ground bond wires are much shorter, starting from outer die pads (22) and ending at power/ground rings (23, 24, 25). For high speed differential signal pairs, there are power/ground wires referred to as dedicated shields, on each side of the pair. Shields extend all the way to the bond finger pad rows where the pair ends.
According to the design rules, referring to the loop shown in FIG. 2(b), each bond wire depends on the die pad row and bond finger pad row corresponding to the respective ends of the wires. Once the loop type is found for a bond wire, the height of the wire is defined.
The bond wire structures discussed above meet JEDEC standard specifications. As shown in FIG. 3, each bond wire includes vertical (h2), horizontal (d/8) and diagonal sections (d-d/8), wherein the length of horizontal section is ⅛ of a parameter d measured from the locations of the bond wire end points. Z=0 refers to the bottom plane of the package; h3 is the thickness of the package; h1 is the height of the die and the package; and h2 is the height of bond wire measured from the die pad. Usually, bond wires originating from inner die pads (21) to any row of the bond finger pads (26, 27) have different height from those originating from outer die pads (22). Each bond wire in this modeling is described by the JEDEC standard geometry parameters.
The bond wire arrangements and structures are highly complex. Each signal bond wire can be a neighbor of another signal bond wire or power/ground wire. A signal bond wire can start from an inner die pad or an outer die pad, ending at the inner bond finger pad or outer bond finger pad. Although rules exist in removing some physically unrealistic geometry, the number of possible structures in real wire bond packages is exceedingly large. Therefore, modeling and simulating structures in high speed wire bond designs are essential for a fast and accurate estimate of the signal quality.
In high speed wire bond packages, electrical noise exists between any two bond wires, an undesired signal transition on one bond wire, referenced to as ‘victim’, may be induced by the signal transition on another bond wire, referenced to as ‘aggressor’. The existence of other bond wires affects the noise level. Parasitic L and C couplings between a victim bond wire and its aggressor are dominant in determining the noise on the victim wire. The inductance and capacitance couplings are basically electromagnetic (EM) effects existing among wires when currents and voltages add on wires. The EM field around the victim wire is greatly influenced by the distance between the victim-aggressor pair, the type of aggressor, and the existence of neighboring power/ground shields, and the like.
Therefore, there is a need to tackle EM coupling problems in an industrially realistic bond wire configuration for high speed high density bond wire packages that is adaptable for any generic noise analysis tool to promptly compute the noise level in a wire bond design.